A computer system can be fabricated from a wide variety of individual components and devices which enable it to operate and perform many desirable functions. Some of the internal components of a computer system can include a central processing unit (CPU), a computer readable volatile memory unit (e.g., random access memory, static RAM, dynamic RAM, etc.), a computer readable non-volatile memory unit (e.g., read only memory, programmable ROM, flash memory, EPROM, EEPROM, etc.), a computer readable mass data storage device such as a magnetic or optical disk, modem device, graphics hardware, sound hardware, and the like. Furthermore, some of the peripheral devices of a computer system, which increase its overall functionality, can include a display device, a keyboard for inputting alphanumeric characters, a cursor control device (e.g., mouse), a printer, a scanner, speakers, and the like.
In order for the many internal components and peripheral devices which constitute a computer system to interact and perform desirable functions, they are interconnected by communication buses. These communication buses can be point-to-point buses, which are typically used between two components. Or they can be buses which are shared by several components. The advantages of the shared bus approach is that not as many wires are needed to implement communication between components. Furthermore, the routing conditions of the computer system are reduced.
In order for a component or circuit block to communicate over a shared bus within a prior art computer system, a bus interface unit is typically implemented internally within the circuit block. The bus interface unit controls the manner in which the circuit block can access the bus. FIG. 1A is a block diagram of a bus interface unit 104 located within a circuit block 102. This type of implementation is commonly used when connecting an integrated circuit (IC) chip to an external shared bus system, such as a peripheral component interconnect (PCI) bus system. Typically, a bus interface unit of a circuit block is designed to conform to the bus standard for which it will be communicating over. For example, bus interface unit 104 is designed to operate in a particular manner to conform to the bus standard of shared bus 114. Specifically, bus interface unit 104 is designed with an input 112 that is always enabled, meaning that it cannot be switched on or off. Furthermore, output 110 of bus interface unit 104 is controlled by circuit block 102 through the use of a tri-state buffer 106 and an output enable signal 108. Moreover, when circuit block 102 desires to drive a signal on external shared bus 114, it first has to transmit signals requesting permission from an external controller (not shown). Once permission is granted by the external controller, circuit block 102 is commanded to assert output enable signal 108 which controls tri-state buffer 106, thereby enabling output 110 to drive shared bus 114. Therefore, when bus interface unit 104 is designed to conform to the bus standard of shared bus 114, circuit block 102 is able to utilize share bus 114 with other circuit blocks. For example, FIG. 1B is a block diagram showing circuit blocks 102, 120, and 122 having the ability to utilize shared external bus 114 when bus interface units 104, 126, and 128 are designed to conform to the bus standard of shared bus 114.
There is a disadvantage associated with the prior art technique of utilizing an internal bus interface unit within a circuit block in order to communicate over a shared bus. The disadvantage is that the internal bus interface unit circuitry of each circuit block is designed and fabricated specifically to be connected in a fixed manner to a single shared bus 114, as shown in FIG. 1B. An additional constraint of this interconnect scheme is that the bandwidth of shared bus 114 should be greater that the sum of the bandwidth required by circuit blocks 102, 120, and 122. This limitation also dictates that the additional connection of any new circuit block to shared bus 114 typically requires a change in the bandwidth of shared bus 114. Since bandwidth is directly proportional to frequency and width of the bus, a change in bandwidth normally cannot be accomplished without changing either frequency or width. Consequently, either or both of these changes usually requires a redesign of the existing circuit blocks 102, 120, and 122.
Therefore, it would be advantageous to provide a system which enables circuit components of a computer system to be connected in a wide variety of shared bus schemes while remaining substantially unchanged. The present invention provides this advantage.